HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 114

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.2
Intel
Datasheet
114
®
5100 Memory Controller Hub Chipset
1. In addition, BCCTRL.BCSERRE also gates the transmission of ERR_FATAL, NON_FATAL and ERR_COR messages
PEXSTS[7:2,0] - Status Register
The PEXSTS is a 16-bit status register that reports the occurrence of error conditions
associated with the primary side of the “virtual” PCI-to-PCI bridge embedded in the
selected PCI Express* cluster of the MCH.
Device:
Function:
Offset:
received from the PCI Express* interface. See
Bit
2
1
0
(port 0)
(port 0)
if (port
if (port
{RW}
{RW}
{RO}
{RO}
elseif
elseif
endif
endif
Attr
7-2)
7-2)
RW
7-2, 0
0
04h
Default
0
0
0
BME: Bus Master Enable
Controls the ability of the PCI Express* port to forward memory or I/O
transactions.
1: Enables the PCI Express* port to successfully complete the memory or
I/O read/write requests.
0: The Bus Master is disabled. The MCH will treat upstream memory writes/
reads, I/O writes/reads, and MSIs as illegal cycles and return Unsupported
Request Status (equivalent to Master abort) in PCI Express*
Requests other than inbound memory or I/O (e.g., configuration,
outbound) are not controlled by this bit.
The BME is typically used by the system software for operations such as
PCI Hot Plug*, device configuration.
When the CPURESET# signal is asserted during a power good or hard reset
and after the ESI completes its training, the LPC device in the ICH9R (or
other NIC/SIO4 cards could potentially send inbound requests even before
the CPURESET# is deassserted. This corner case is handled by the BME
filtration in the Intel
above rules since BME is reset. However, in general, it is illegal for an I/O
device to issue inbound requests until the CPURESET# has been
deasserted to prevent any possible malfunction in the Intel
Chipset logic.
MSE: Memory Space Enable
Controls the bridge’s response as a target to memory accesses on the
primary interface that address a device that resides behind the bridge in
both the non-prefetchable and prefetchable memory ranges (high/low) or
targets a memory-mapped location within the bridge itself
1: Enables the Memory and Prefetchable memory address ranges (MMIO)
defined in the MBASE/MLIM, PMBASE/PMLIM, PMBU/PMLU registers.
0: Disables the entire memory space seen by the PCI Express* port on the
primary side (MCH). Requests will then be subtractively claimed by the
ICH9R. For port 0, this bit is hardwired to 0 since the ESI is not a PCI-to-
PCI bridge.
IOAE: Access Enable
1: Enables the I/O address range defined in the IOBASE and IOLIM
registers.
0: Disables the entire I/O space seen by the PCI Express* port on the
primary. Requests will be then be subtractively claimed by the ICH9R.
For port 0, this bit is hardwired to 0 since the ESI is not a PCI-to-PCI
bridge.
Section 3.8.8.28, “BCTRL[7:2] - Bridge Control Register.”
®
5100 MCH Chipset’s PCI Express* port using the
Intel
®
5100 MCH Chipset—Register Description
Description
Order Number: 318378-005US
®
5100 MCH
July 2009