HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 248

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.23.6
3.11.23.7
3.11.23.8
Intel
Datasheet
248
®
5100 Memory Controller Hub Chipset
CHANCMP[3:0]: Channel Completion Address Register
This register specifies the address where the DMA channel writes the completion status
upon completion or an error condition, i.e., it writes the contents of the CHANSTS
register to the destination as pointed by the CHANCMP register. The channel completion
write is sent after the DMA Engine has updated all its internal states following the
transfer. The CHANCMP address will be checked and an error will be set by the DMA
Engine during execution if it is found illegal. The CHANCMP error will be recorded in
FERR/NERR*DMA12 register fields and also in the CHANERR.Cmp_addr_err fields.
1. This prevents straddling across cache lines since the contents of the CHANSTS registers are 8-bytes wide.
CDAR[3:0]: Current Descriptor Address Register
The software should issue only 32-bit (DW) reads to the CDAR register. The upper DW
is latched when the lower DW is read by software and the chipset will ensure the data
consistency for the split reads. See description in
CHANERR[3:0] - Channel Error Register
The Channel Error Register records the error conditions occurring within a given DMA
channel. All errors in this register from bits 14:0 are treated as affiliated errors while
bits 15:14 are read only as Intel
soft errors. For all Fatal errors (affiliated), the DMA Engine will not resume from the
Halted state (or start a new operation) until the software handles the source of the
error, resetting the respective registers and then clearing the associated error bits in
the CHANERR register. If there are affiliated errors in CHANERR and the Start DMA is
asserted, then the CHANERR.chancmd_err bit will be set.
Offset:
63:3
2:0
Offset:
63:0
Offset:
31:16
15
14
Bit
Bit
Bit
RW
RV
RO
RV
RO
RO
Attr
Attr
Attr
218h, 198h, 118h, 98h
220h, 1A0h, 120h, A0h
228h, 1A8h, 128h, A8h
0h
0h
0h
Default
Default
0h
0
0
Default
Chan_cmp_addr: Channel Completion Address
This 64-bit field specifies the address where the DMA Engine writes the completion
status (CHANSTS). This address can fall within system memory or memory-mapped
I/O space but should be 8-byte aligned
Reserved
Cur_desc_addr: Current Descriptor Address
This 64-bit field denotes the address of the current Descriptor (i.e., the descriptor
that is currently being processed by the DMA channel).
Reserved
Unaffil_err: Unaffiliated Error
The Intel
Soft_err: Soft Error
The Intel
®
®
®
5100 MCH Chipset does not detect unaffiliated Errors.
5100 MCH Chipset does not implement soft error detection.
5100 MCH Chipset does not detect unaffiliated or
Intel
Description
Description
Section 3.11.23.3
Description
®
5100 MCH Chipset—Register Description
1
.
Order Number: 318378-005US
July 2009