HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 222

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.2
Intel
Datasheet
222
®
5100 Memory Controller Hub Chipset
PEXSTS: PCI Status Register
The PCI Status register follows a subset of the PCI Local Bus Specification, Rev. 2.3.
This register maintains compatibility with PCI configuration space. Since this register is
part of the standard PCI header, there is a PEXSTS register per PCI function.
Device:
Function:
Offset:
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Bit
RWC
RWC
RO
RWC
RWC
RO
RWC
RO
RV
RO
RO
RO
RV
Attr
8
0
06h
0
0
0
0
0
00
0
0
0
0
1
0
000
Default
DPE: Detected Parity Error
This bit is set when the DMA Engine device receives an uncorrectable data error or
Address/Control parity errors regardless of the Parity Error Enable bit (PERRE). This
applies only to parity errors that target the DMA Engine device (inbound/outbound
direction). The detected parity error maps to B1, F6, M2 and M4 (uncorrectable
data error from FSB, Memory or internal sources). The DMA Engine also records the
data parity error in bit[6] (Cdata_par_err)of the CHANERR register. Refer to
Section 5.24, “Error
SSE: Signaled System Error
1: The DMA Engine device reported internal FATAL/NON FATAL errors (DMA0-15)
through the ERR[2:0] pins with SERRE bit enabled. Software clears this bit by
writing a ‘1’ to it.
0: No internal DMA Engine device port errors are signaled.
RMA: Received Master Abort Status
This field is hardwired to 0 as there is no Master Abort for the DMA operations
RTA: Received Target Abort Status
This field is hardwired to 0 as there is no Target Abort for the DMA operations
STA: Signaled Target Abort Status:
This field is hardwired to 0
DEVSELT: DEVSEL# Timing:
This bit does not apply to the DMA Engine Device.
MDIERR: Master Data Integrity Error
This bit is set by the DMA Engine device if the Parity Error Enable bit (PERRE) is set
and it receives error B1, F2, F6, M2 and M4 (uncorrectable data error or Address/
Control parity errors or an internal failure). If the PERRRSP bit in the
3.11.1, “PEXCMD: PCI Command Register”
Section 5.24, “Error
FB2B: Fast Back-to-Back Capable
Not applicable to DMA Engine. Hardwired to 0.
Reserved
66MHZCAP: 66 MHz capable
Not applicable to DMA Engine. Hardwired to 0.
CAPL: Capability List Implemented:
This bit indicated that the DMA Engine device implements a PCI Capability list. See
CAPPTR at offset 34h
INTxST: INTx State
This bit is set by the hardware when the DMA Engine device issues a legacy INTx
(pending) and is reset when the INTx is deasserted.
The INTx status bit should be deasserted when all the relevant
status bits/events viz DMA errors/completions that require
legacy interrupts are cleared by software.
Reserved
List”.
List”.
Intel
Description
®
5100 MCH Chipset—Register Description
is cleared, this bit is never set. Refer to
Order Number: 318378-005US
Section
July 2009