HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 290

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.2.8.7
5.2.9
Table 91.
5.2.10
Intel
Datasheet
290
®
5100 Memory Controller Hub Chipset
Disabling Open Loop Throttling
The following registers in the Intel
throttling if software desires to turn off throttling.
Above changes force Open loop throttling off.
Electrical Throttling
Electrical throttling is a mechanism that limits the number of activations (burstiness)
within a very short time interval that would otherwise cause silent data corruption on
the DIMMs. Electrical throttling is enabled by setting the MTR.ETHROTTLE bit defined in
Section 3.9.1.6, “MTR[1:0][5:0] - Memory Technology
per rank basis per channel as to whether electrical throttling should be used.
The per rank electrical throttling limit is four activations per 37.5 ns window (JEDEC
consensus) and is summarized in
DIMM Technology”
per T
Electrical Throttle Window as Function of DIMM Technology
1. Maximum four activations per rank is allowed within the window.
The MTR.ETHROTTLE registers bit enables/disables electrical throttling. The DRTA.TFAW
configuration register field limits the number of activations per sliding electrical throttle
window. A shift register whose length (max 20) is determined by TFAW is used to
record activations to each rank. New activations shift in a ‘1’ while old activations are
“dropped” at the end of the TFAW window. If the limit is reached, then further
activations to the rank are blocked until the count falls below the limit. The Electrical
throttling logic in the MC masks off the end bits for the DIMM technologies that require
fewer clocks. As an example, if the DIMM technology used is DDR2-667, then it can
allow four activations within the last 13 clocks, the remaining seven bits are masked
(forced to 0) so they do not prevent activations.
Normal Self-refresh Entry
The Intel
under control of the power management system (in response to a BIOS request). The
sequence of operations involved in the operation is as follows.
Conservative
(safe mode)
1. MCH Power Management asserts Queue Flush - at this point, the system is
2. Memory Controller (MC) responds by blocking all new requests
3. MC starts to flush posted write Queue
4. Both read and write Queues are drained
• THRTHIGH.THRTHIGHLM = 0
• THRTLOW.THRTLOWLM = 0
• GBLACT.BLACTLM = 0
DDR2-533
DDR2-667
Modes
DIMM
committed to a power cycle (assertion of power good reset)
RC
(RAS cycle time) is around 4xT
®
5100 MCH Chipset puts the DIMMs into self-refresh for S3 power mode
Intel
for various DIMM technologies. For DDR2, the number of activations
®
5100 MCH Chipset Core:
DIMM clock Ratio
All
All
All
Table 91, “Electrical Throttle Window as Function of
®
5100 MCH Chipset can be initialized to disable
RC
/T
FAW
Intel
=4x60/37.5=6.4.
®
5100 MCH Chipset—Functional Description
Registers”. These bits occur on a
Electrical Throttle Window
(memory clocks per rank)
Order Number: 318378-005US
10
13
20
1
July 2009