HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 38

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 5.
Intel
Datasheet
38
®
5100 Memory Controller Hub Chipset
Processor Front Side Bus 0 Signals (Sheet 4 of 5)
FSB0DSTBP[3:0]#
FSB0DSTBN[3:0]#
FSB0HIT#
FSB0HITM#
FSB0LOCK#
FSB0MCERR#
FSB0REQ[4:0]#
FSB0RESET#
Signal Name
I/O
I/O
I/O
I
I/O
I/O
O
Type
Processor 0 Differential Host Data Strobes:
The differential source synchronous strobes used to transfer FSB0D[63:0]# and
FSB0DBI[3:0]# at the 4x transfer rate.
Processor 0 Cache Hit:
FSB0HIT# along with FSB0HITM# convey transaction snoop operation results.
Any FSB agent may assert both FSB0HIT# and FSB0HITM# together to indicate
that it requires a snoop stall to extend the snoop window. The stall an be
continued by reasserting FSB0HIT# and FSB0HITM# together. The FSB0HIT#
signal indicates that a caching agent holds an unmodified version of the
requested line.
Processor 0 Cache Hit Modified:
FSB0HITM# along with FSB0HIT# convey transaction snoop operation results.
Any FSB agent may assert both FSB0HITM# and FSB0HIT# together to indicate
that it requires a snoop stall to extend the snoop window. The stall an be
continued by reasserting FSB0HITM# and FSB0HIT# together. The FSB0HITM#
signal indicates that a caching agent holds a modified version of the requested
line.
Processor 0 Lock:
FSB0LOCK# indicates to the system that a transaction must occur atomically.
For a locked sequence of transactions, FSB0LOCK# is asserted from the
beginning of the first transaction to the end of the last transaction.
When the priority agent asserts FSB0BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes FSB0LOCK# deasserted. This
enables symmetric agents to retain ownership of the processor FSB throughout
the bus locked operation and ensure the atomicity of lock.
Processor 0 Machine Check Error:
FSB0MCERR# is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by all processor FSB agents.
FSB0MCERR# assertion conditions are configurable at a system level. For more
details regarding machine check architecture, refer to the Intel
Architectures Software Developer’s Manual, Volume 3: System Programming
Guide.
Processor 0 Bus Request Command:
FSB0REQ[4:0]# define the attributes of the request. FSB0REQ[4:0]# are
transferred at 2x rate and are source synchronous to FSB0ADSTB[1:0]#. They
are asserted by the requesting agent during both halves of request phase. In
the first half, the signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type. Refer to the
FSB0AP[1:0]# signal description for details on parity checking of these signals.
Processor 0 Reset:
FSB0RESET# is an output from the MCH. The MCH asserts FSB0RESET# while
RESETI# (PLTRST# from ICH9R) is asserted and for approximately 1 ms after
RESETI# is deasserted. The FSB0RESET# allows the processors to begin
execution in a known state and invalidates their internal caches without writing
back any of their contents.
FSB0D[31:16]#
FSB0D[47:32]#
FSB0D[63:48]#
FSB0D[15:0]#
Data Group
FSB0DSTB{P/N}[0]#
FSB0DSTB{P/N}[1]#
FSB0DSTB{P/N}[2]#
FSB0DSTB{P/N}[3]#
Data Strobe
Intel
Description
®
5100 MCH Chipset—Signal Description
Bus Inversion Signal
Order Number: 318378-005US
FSB0DBI[0]#
FSB0DBI[1]#
FSB0DBI[2]#
FSB0DBI[3]#
®
64 and IA-32
July 2009