MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 121

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
BCLR n,opr8a
BCS rel
BEQ rel
BGE rel
BGND
BGT rel
BHCC rel
BHCS rel
BHI rel
BHS rel
BIH rel
BIL rel
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
BLE rel
BLO rel
BLS rel
BLT rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Source
Form
Clear Bit n in Memory
Branch if Carry Bit Set
(Same as BLO)
Branch if Equal
Branch if Greater Than or
Equal To
(Signed Operands)
Enter Active Background
if ENBDM = 1
Branch if Greater Than
(Signed Operands)
Branch if Half Carry Bit
Clear
Branch if Half Carry Bit
Set
Branch if Higher
Branch if Higher or Same
(Same as BCC)
Branch if IRQ Pin High
Branch if IRQ Pin Low
Bit Test
Branch if Less Than
or Equal To
(Signed Operands)
Branch if Lower
(Same as BCS)
Branch if Lower or Same
Branch if Less Than
(Signed Operands)
Branch if Interrupt Mask
Clear
Branch if Minus
Branch if Interrupt Mask
Set
Branch if Not Equal
Branch if Plus
Branch Always
Operation
Table 7-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
Commands Until GO, TRACE1, or
MC9S08AW60 Data Sheet, Rev 2
Waits For and Processes BDM
(CCR Updated but Operands
Branch if (Z) | (N ⊕ V) = 0
Branch if (Z) | (N ⊕ V) = 1
Branch if (C) | (Z) = 1
Branch if (C) | (Z) = 0
Branch if (N ⊕ V ) = 1
Branch if IRQ pin = 1
Branch if IRQ pin = 0
Branch if (N ⊕ V) = 0
Branch if (C) = 1
Branch if (C) = 1
Branch if (Z) = 1
Branch if (H) = 0
Branch if (H) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (Z) = 0
Branch if (N) = 0
Branch if (I) = 0
Branch if (I) = 1
Description
Not Changed)
(A) & (M)
Mn ← 0
TAGGO
No Test
V H I N Z C
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
0 – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
Chapter 7 Central Processor Unit (S08CPUV2)
on CCR
Effect
↕ ↕
–
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
REL
REL
INH
REL
REL
REL
REL
REL
REL
REL
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
9ED5
9EE5
1D
C5
D5
2C rr
2D rr
1B
2E rr
A5
B5
E5
2B rr
2A rr
11
13
15
17
19
1F
25 rr
27 rr
90 rr
82
92 rr
28 rr
29 rr
22 rr
24 rr
2F rr
F5
93 rr
25 rr
23 rr
91 rr
26 rr
20 rr
dd
dd
dd
dd
dd
dd
dd
dd
ii
dd
hh ll
ee ff
ff
ee ff
ff
5+
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
3
3
2
3
4
4
3
3
5
4
3
3
3
3
3
3
3
3
3
3
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