MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 153

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

8.5.4
In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate)
reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim
function to fine tune the frequency based on an external reference signal.
After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately
8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (f
The clock scheme will be FLL engaged, internal (FEI). So
Solving for N / R gives:
A trim procedure will be required to hone the frequency to exactly 5.4 MHz. An example of the trim
procedure is shown in example #4.
The values needed in each register to set up the desired operation are:
ICGC1 = $28 (%00101000)
ICGC2 = $31 (%00110001)
ICGS1 = $xx
ICGS2 = $xx
ICGFLTLU/L = $xx
Freescale Semiconductor
Bit 7
Bit 6
Bit 5
Bits 4:3 CLKS
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6:4 MFD
Bit 3
Bit 2:0 RFD
This is read only except for clearing interrupt flag
This is read only; good idea to read this before performing time critical operations
Not used in this example
Example #3: No External Crystal Connection, 5.4 MHz Bus
Frequency
N / R = 10.8 MHz /(243/7 kHz * 64) = 4.86 ; We can choose N = 10 and R = 2.
HGO
RANGE
REFS
OSCSTEN 0
LOCD
LOLRE
LOCRE
f
ICGOUT
0
0
1
01
0
0
0
011 Sets the MFD multiplication factor to 10
0
001 Sets the RFD division factor to ÷2
= (f
Configures oscillator for low power
Configures oscillator for low-frequency range; FLL prescale factor is 64
Oscillator using crystal or resonator requested (bit is really a don’t care)
FLL engaged, internal reference clock mode
Disables the oscillator
Loss-of-clock enabled
Unimplemented or reserved, always reads zero
Generates an interrupt request on loss of lock
Generates an interrupt request on loss of clock
IRG
/ 7) * P * N / R ; P = 64, f
MC9S08AW60 Data Sheet, Rev 2
IRG
= 243 kHz
Chapter 8 Internal Clock Generator (S08ICGV4)
Bus
).
Eqn. 8-5
Eqn. 8-6
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