MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 286
MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW32CFGE.pdf
(324 pages)
Specifications of MC9S08AW32CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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Appendix A Electrical Characteristics and Timing Specifications
Solving equations 1 and 2 for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving equations 1 and 2 iteratively for any value of T
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
286
D
(at equilibrium) for a known T
Num C
1
2
3
4
Human Body
Model
Machine Model
Latch-Up
ESD Protection and Latch-Up Immunity
Model
C Human Body Model (HBM)
C Machine Model (MM)
C Charge Device Model (CDM)
C Latch-up Current at T
Series Resistance
Storage Capacitance
Number of Pulse per pin
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Table A-5. ESD and Latch-Up Protection Characteristics
Table A-4. ESD and Latch-up Test Conditions
K = P
A
Rating
A
= 125°C
. Using this value of K, the values of P
D
MC9S08AW60 Data Sheet, Rev 2
× (T
Description
A
+ 273°C) + θ
A
JA
.
× (P
Symbol
V
V
D
V
I
HBM
CDM
LAT
)
MM
2
Symbol
R1
R1
—
—
C
C
± 2000
± 200
± 500
± 100
Min
D
and T
J
Value
1500
–2.5
100
200
can be obtained by
7.5
3
0
3
Freescale Semiconductor
Max
—
—
—
—
Unit
pF
pF
Ω
Ω
V
V
Unit
mA
V
V
V
Eqn. A-3
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