MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 165

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10
Timer/PWM (S08TPMV2)
10.1
The MC9S08AW60 Series includes two independent timer/PWM (TPM) modules which support
traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on
each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned
PWM functions. In each of these two TPMs, timing functions are based on a separate 16-bit counter with
prescaler and modulo features to control frequency and range (period between overflows) of the time
reference. This timing system is ideally suited for a wide range of control applications, and the
center-aligned PWM capability on the 3-channel TPM extends the field of applications to motor control in
small appliances.
The use of the fixed system clock, XCLK, as the clock source for either of the TPM modules allows the
TPM prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This option is only available
if the ICG is configured in FEE mode and the proper conditions are met (see
Frequency
BUSCLK.
10.2
The timer system in the MC9S08AW60 Series includes a 6-channel TPM1 and a separate 2-channel
TPM2. Timer system features include:
Freescale Semiconductor
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A total of eight channels:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system
clock, or an external pin:
— Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
— External clock inputs TPM1CLK for TPM1 and TPM2CLK for TPM2 (only available in
16-bit free-running or up/down (CPWM) count operation
16-bit modulus register to control counter range
Timer system enable
One interrupt per channel plus a terminal count interrupt for each TPM module
Introduction
Features
Clock”). In all other ICG modes this selection is redundant because XCLK is the same as
64-pin package)
MC9S08AW60 Data Sheet, Rev 2
Section 8.4.11, “Fixed
165