MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 76

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 5 Resets, Interrupts, and System Configuration
5.9.5
This register is used to control the MCLK clock output.
76
Reset
Reset
MCSEL
STOPE
COPE
COPT
Field
Field
MPE
2:0
7
6
5
4
W
W
R
R
System MCLK Control Register (SMCLK)
COPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (2
1 Long timeout period selected (2
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See
1
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
COPT
1
0
0
6
6
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-6. SMCLK Register Field Descriptions
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Register Field Descriptions
STOPE
0
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
18
13
cycles of BUSCLK).
cycles of BUSCLK).
Equation
MPE
1
0
4
4
5-1.
Description
Description
3
0
0
3
0
0
0
0
0
2
2
Freescale Semiconductor
MCSEL
1
0
1
1
Eqn. 5-1
1
0
0
0