MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 145
MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08AW32CFGE.pdf
(324 pages)
Specifications of MC9S08AW32CFGE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
32KB
Lead Free Status / RoHS Status
Compliant
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8.4.9
The reference clock and the DCO clock are monitored under different conditions (see
the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum
frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls
below a certain frequency, f
LOCS will remain set until it is acknowledged or until the MCU is reset. LOCS is cleared by reading
ICGS1 then writing 1 to ICGIF (LOCRE = 0), or by a loss-of-clock induced reset (LOCRE = 1), or by any
MCU reset.
If the ICG is in FEE, a loss of reference clock causes the ICG to enter SCM, and a loss of DCO clock causes
the ICG to enter FBE mode. If the ICG is in FBE mode, a loss of reference clock will cause the ICG to
enter SCM. In each case, the CLKST and CLKS bits will be automatically changed to reflect the new state.
If the ICG is in FEE mode when a loss of clock occurs and the ERCS is still set to 1, then the CLKST bits
are set to 10 and the ICG reverts to FBE mode.
A loss of clock will also cause a loss of lock when in FEE or FEI modes. Because the method of clearing
the LOCS and LOLS bits is the same, this would only be an issue in the unlikely case that LOLRE = 1 and
LOCRE = 0. In this case, the interrupt would be overridden by the reset for the loss of lock.
Freescale Semiconductor
1
2
(CLKST = 00)
(CLKST = 01)
(CLKST = 10)
(CLKST = 11)
If ENABLE is high (waiting for external crystal start-up after exiting stop).
DCO clock will not be monitored until DCOS = 1 upon entering SCM from off or FLL bypassed external mode.
Mode
FLL Loss-of-Clock Detection
SCM
FBE
FEE
FEI
Off
0X or 11
CLKS
0X
0X
10
10
10
10
11
11
10
10
11
LOR
Table 8-8. Clock Monitoring (When LOCD = 0)
and f
REFST
X
X
X
X
X
X
0
1
0
1
0
1
LOD
MC9S08AW60 Data Sheet, Rev 2
, respectively, the LOCS status bit will be set to indicate the error.
Forced High
Forced High
Forced Low
Forced Low
Real-Time
Forced Low
Forced Low
Real-Time
Real-Time
Real-Time
Real-Time
Real-Time
ERCS
1
External Reference
Monitored?
Clock
Yes
Yes
Yes
Yes
Yes
Yes
Chapter 8 Internal Clock Generator (S08ICGV4)
No
No
No
No
No
No
(1)
Table
Monitored?
DCO Clock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
(2)
(2)
(2)
8-8). Provided
2
145
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