MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 51

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

4.4.1
Features of the FLASH memory include:
4.4.2
Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must
be written to set the internal clock for the FLASH module to a frequency (f
200 kHz (see
once, so normally this write is done during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/f
program and erase pulses. An integer number of these timing pulses are used by the command processor
to complete a program or erase command.
Table 4-5
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Freescale Semiconductor
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FLASH Size
— MC9S08AW60 — 63280 bytes (124 pages of 512 bytes each)
— MC9S08AW48 — 49152 bytes (96 pages of 512 bytes each)
— MC9S08AW32 — 32768 bytes (64 pages of 512 bytes each)
— MC9S08AW16 — 16384 bytes (32 pages of 512 bytes each)
Single power supply program and erase
Command interface for fast program and erase operation
Up to 100,000 program/erase cycles at typical voltage and temperature
Flexible block protection
Security feature for FLASH and RAM
Auto power-down for low-frequency read accesses
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
Features
Program and Erase Times
FCLK
1
2
Section 4.6.1, “FLASH Clock Divider Register
Byte program
Byte program (burst)
Page erase
Mass erase
Excluding start/end overhead
Because the page and mass erase times can be longer than the COP watchdog timeout, the
COP should be serviced during any software erase routine.
). The time for one cycle of FCLK is t
Parameter
Table 4-5. Program and Erase Times
MC9S08AW60 Data Sheet, Rev 2
Cycles of FCLK
20,000
4000
9
4
FCLK
FCLK
) is used by the command processor to time
= 1/f
(FCDIV)”). This register can be written only
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
FCLK
100 ms
20 ms
20 μs
45 μs
) between 150 kHz and
1
2
2
Chapter 4 Memory
51