MC9S08AW32CFGE Freescale, MC9S08AW32CFGE Datasheet - Page 84

• Manufacturer Part Number: MC9S08AW32CFGE
• Manufacturer: Freescale

Specifications of MC9S08AW32CFGE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
pullup enable (PTDPE), slew rate control (PTDSE), and drive strength select (PTDDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port D general-purpose I/O are shared with the ADC, KBI, and TPM1 and TPM2 external clock inputs.
When any of these shared functions is enabled, the direction, input or output, is controlled by the shared
function and not by the data direction register of the parallel I/O port. When a pin is shared with both the
ADC and a digital peripheral function, the ADC has higher priority. For example, in the case that both the
ADC and the KBI are configured to use PTD7 then the pin is controlled by the ADC module.
Refer to
external clock inputs.
Refer to
port D pins as analog inputs.
Refer to
keyboard inputs.
6.3.5
Port E pins are general-purpose I/O pins. Parallel I/O function is controlled by the port E data (PTED) and
data direction (PTEDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTEPE), slew rate control (PTESE), and drive strength select (PTEDS) are located in the
high page registers. Refer to
general-purpose I/O control and
Port E general-purpose I/O is shared with SCI1, SPI, and TPM1 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to
port E pins as SCI pins.
Refer to
pins as SPI pins.
Refer to
channel pins.
84
Port E
Chapter 10, “Timer/PWM
Chapter 14, “Analog-to-Digital Converter
Chapter 9, “Keyboard Interrupt
Chapter 11, “Serial Communications Interface
Chapter 12, “Serial Peripheral Interface
Chapter 10, “Timer/PWM
Port E
MCU Pin:
SPSCK1
PTE7/
Bit 7
Section 6.4, “Parallel I/O
Section 6.4, “Parallel I/O
Section 6.5, “Pin
Section 6.5, “Pin
MOSI1
PTE6/
(S08TPMV2)” for more information about using port D pins as TPM
(S08TPMV2)”
6
MC9S08AW60 Data Sheet, Rev 2
Figure 6-5. Port E Pin Names
(S08KBIV1)” for more information about using port D pins as
MISO1
PTE5/
5
(S08SPIV3)”
Control” for more information about pin control.
Control” for more information about pin control.
(S08ADC10V1)” for more information about using
for more information about using port E pins as TPM
Control” for more information about
Control” for more information about
PTE4/
SS1
(S08SCIV2)”
4
for more information about using port E
TPM1CH1
PTE3/
3
for more information about using
TPM1CH0
PTE2/
2
Freescale Semiconductor
PTE1/
RxD1
1
PTE0/
TxD1
Bit 0