PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 158

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

5.1
5.1.1
The receive PLL readjusts, if the integrator function is enabled (TR_CONF1.RPLL_INTD
= ’0’) if six consecutive pulses on the line interface deviate in the same direction. If the
integrator function is disabled by setting TR_CONF1.RPLL_INTD to’1’ this is done after
the deviation of every pulse. Adjusting on the positive and negative pulses is done by
adding/subtracting 1 XTAL from/to the DCL clock.
5.1.2
The transmit clock of the line interface is derived from the receive clock of the line
interface.
5.1.3
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers
are involved.
•
Figure 74Clock waveforms
Data Sheet
FSC
DCL
BCL
Jitter
Jitter on IOM-2
Jitter on the Line Interface
Jitter on MCLK
158
PSB 21373
2002-05-13