PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 32

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

PSB 21373
2.2
IOM-2 Interface
The SCOUT-DX supports the IOM-2 interface in terminal mode with single clock and
double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The
rising edge of FSC indicates the start of an IOM-2 frame. The FSC signal is generated
by the receive DPLL which synchronizes to the received line frame. The DCL and the
BCL output clock signals synchronize the data transfer on both data lines. The DCL is
twice the bit rate, the BCL output rate is equal to the bit rate. The bits are shifted out with
the rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle. The BCL clock together with the two serial data strobe signals (SDS1,
SDS2) can be used to connect time slot oriented standard devices to the IOM-2
interface.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register. The BCL clock output can be enabled separately with the EN_BCL bit.
The clock rate or frequency respectively of the IOM-signals in TE mode are:
DD, DU: 768 kbit/s
DCL: 1536 kHz (double clock rate); 768 kHz (single clock rate if DIS_TR = ’1’)
FSC: 8 kHz.
If the transceiver is disabled (TR_CONF.DIS_TR) the DCL and FSC pins become input
and the HDLC and codec parts can still work via IOM-2. In this case it can be selected
with the clock mode bit (IOM_CR.CLKM) between a double clock and a single clock
input.
Note: One IOM-2 frame has to consist of a multiple of 16 (8) DCL clocks for a double
(single) clock selection.
FSC
DCL
BCL
bcl
Figure 10 Clock waveforms
Data Sheet
32
2002-05-13