PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 67

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
2.3.2
The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which
is used to synchronize the PLL to the frame received from the line interface. The PLL
outputs the FSC-signal as well as the 1.536-MHz double bit clock signal and the 768-kHz
bit clock.
2.3.3
Figure 34
Data Delay between IOM and Line Interface
The lOM-interface B-channels are used to convey the two 64-kbit/s user channels in both
directions.
Only in the activated states the data is transferred transparently. In all other states logical
’1’s are transmitted to the IOM interface.
Line
FSC
DU
DD
B1
B1
B1
B2 D
B2 D
Transceiver Timing
Data Transfer and Delay between IOM and Line Interface
B2
D
B1 B2D
B1
B1
B1
B2 D
B2 D
B2
D
B1 B2D
B1
B1
67
B1
B2 D
B2 D
B2
D
B1 B2D
B1
B1
B1
B2 D
B2 D
B2
D
B1 B2D
PSB 21373
line_iom_d
2002-05-13