PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 89

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
Figure 46
RFIFO Operation
EXMR.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAH.RPF
is set.
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTA)
is appended.
Meanwhile two
more short frames
have been
received.
FIFO.
HDLC
Receiver
HDLC
Receiver
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDR.RMC.
This causes the space occupied by the 16 bytes being
released.
RAM
RAM
RSTA
RSTA
RSTA
µP
µP
32
16
32
16
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
RFBS=01
RFBS=11
RFACC
RFACC
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDR.RMC command.
Following CMDR.RMC
the 4 bytes of the
last block are
deleted.
RMC
89
EXMR.RFBS=01
RMC
Receiver
HDLC
Receiver
HDLC
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
RAM
RAM
RSTA
RSTA
RSTA
µP
32
16
32
16
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
PSB 21373
RFBS=01
RFBS=01
RFACC
RFACC
2002-05-13