PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 77

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

PSB 21373
2.3.4.2
External Layer-1 State machine
Instead of using the integrated layer-1 state machine it is also possible to implement the
layer-1 state machine completely in software.
The internal layer-1 state machine can be disabled by setting the L1SW bit in the
TR_CONF0 register (see chapter 7.2.6) to ’1’.
The transmitter is completely under control of the microcontroller via register TR_CMD
(see chapter 7.2.5).
The status of the receiver is stored in register TR_STA (see chapter 7.2.4) and has to
be evaluated by the microcontroller. This register is updated continuously. If not masked
a RIC interrupt (see chapter 7.2.6) is generated by any change of the register contents.
The interrupt is cleared after a read access to this register.
Data Sheet
77
2002-05-13