PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 80

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

2.3.5
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM interface, are stopped. The data lines and the FSC are ’high’, whereas
DCL is ’low’ and BCL is ’high’.
An activation initiated from the exchange side (any signal detected on the line interface)
will have the consequence that clock signals are provided automatically if the bit LDD of
register TR_CONF0 is set to ’0’.
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
2.3.6
The layer-1 part of the SCOUT-DX can be enabled/disabled by configuration with the two
bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
By default all layer-1 functions are enabled (DIS_TR = ’0’, DIS_TX = ’0’). If DIS_TX = ’1’
only the transmit buffers are disabled. The receiver will monitor for incoming calls in this
configuration.
If DIS_TR = ’1’ all layer-1 functions are disabled including the level detection circuit of
the receiver. In this case the power consumption of the layer-1 is reduced to a minimum.
The HDLC controller and codec part can still operate via IOM-2. The DCL and FSC pins
become inputs.
Data Sheet
Level Detection Power Down
Transceiver Enable/Disable
80
PSB 21373
2002-05-13