PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 207

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PSB21373HV1.1XT

Manufacturer Part Number
PSB21373HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21373HV1.1XT

Lead Free Status / RoHS Status
Compliant
Data Sheet
7.3.18
Value after reset: 00
MOCR
MRE
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
1: MR is internally controlled according to the MONITOR channel protocol. In addition,
MIE
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled according to the MONITOR channel
a packet (if MRE = 1).
the MDR interrupt is enabled for all received bytes according to the MONITOR
channel protocol (if MRE = 1).
protocol.
MOCR - MONITOR Control Register
7
MRE
... MONITOR Receive Interrupt Enable
... MR Bit Control:
... MONITOR Interrupt Enable
... MX Bit Control
MRC
H
MIE
MXC
207
0
0
0
0
0
RD/WR (5E
PSB 21373
2002-05-13
H
)

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