PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 172

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

7.1.6
Value after reset: 00
CMDR
RMC
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFO may be released.
RRES
HDLC receiver is reset, the RFIFO is cleared of any data.
STI
The hardware timer is started when STI is set to one. The timer may be stopped by a
write to the TIMR register.
XTF
After having written up to 16 or 32 bytes (EXMR.XFBS) in the XFIFO, the microcontroller
initiates the transmission of a transparent frame by setting this bit to ’1’. Except in the
extended transparent mode the opening flag is automatically added to the message.
XME
By setting this bit to ’1’ the microcontroller indicates that the data block written last in the
XFIFO completes the corresponding frame. Except in the extended transparent mode
the transmission is terminated by appending the CRC and the closing flag sequence to
the data.
XRES
HDLC transmitter is reset and the XFIFO is cleared of any data. This command can be
used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFO and the
Data Sheet
appropriate Transmit Command (XTF) has to be written to the CMDR register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAH).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically except in the extended mode.
CMDR - Command Register
7
RMC RRES
... Receive Message Complete
... Receiver Reset
... Start Timer
... Transmit Transparent Frame
... Transmit Message End
... Transmitter Reset
H
0
STI
172
XTF
0
XME XRES
0
PSB 21373
2002-05-13
WR (21
H
)