PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 99

• Manufacturer Part Number: PSB21373HV1.1XT
• Manufacturer: Infineon Technologies

Specifications of PSB21373HV1.1XT

• Lead Free Status / RoHS Status: Compliant

Data Sheet
The following description gives an example for the transmission of a 76 byte frame with
a selected block size of 32 byte (EXMR:XFBS=0):
• The host writes 32 bytes to the XFIFO, issues an XTF command and waits for an XPR
• The HDLC controller immediately issues an XPR interrupt (as remaining XFIFO space
• Due to the XPR interrupt the host writes the next 32 bytes to the XFIFO, followed by
• As soon as the last byte of the first block is transmitted, the HDLC controller issues an
• The host writes the remaining 12 bytes of the frame to the XFIFO and issues the XTF
• After the last byte of the frame has been transmitted the HDLC controller releases an
Figure 51
Transmission Sequence, Example
Transmit
Frame
interrupt in order to continue with entering data.
is not used) and starts transmission.
the XTF command, and waits for XPR.
XPR interrupt (XFIFO space of first data block is free again) and continues
transmitting the second block.
command together with XME to indicate that this is the end of frame.
XPR interrupt and the host may proceed with transmission of a new frame.
32 Bytes
WR
XTF
XPR
32 Bytes
WR
32
XTF
XPR
CPU Interface
IOM Interface
76 Bytes
12 Bytes
99
WR
XTF+XME
32
12
XPR
PSB 21373
2002-05-13
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