LPC1850FET256,551 NXP Semiconductors, LPC1850FET256,551 Datasheet - Page 31

• Manufacturer Part Number: LPC1850FET256,551
• Description: MCU 32BIT ARM CORTEX M3 256BGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1850FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, QEI, SD/MMC, SPI, SSI, SSP, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 200K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: LPC1850
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 200 KB
• Interface Type: SPI Flash (SPIFI), USB, Ethernet, LCD, External Memory Controller, I2C
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 6
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6682

NXP Semiconductors
LPC1850_30_20_10
Objective data sheet
Fig 3.
(1) Not available on all parts (see
System
AHB MULTILAYER MATRIX
AHB multilayer matrix master and slave connections
bus
= master-slave connection
7.4.1 Features
I-code
CORTEX-M3
TEST/DEBUG
INTERFACE
7.3 AHB multilayer matrix
7.4 Nested Vectored Interrupt Controller (NVIC)
bus
ARM
D-code
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
bus
•
•
•
•
•
•
Controls system exceptions and peripheral interrupts.
In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts.
32 programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
Software interrupt generation.
0
GPDMA
Table
1
All information provided in this document is subject to legal disclaimers.
2).
ETHERNET
Rev. 1.2 — 17 February 2011
(1)
USB0
(1)
USB1
(1)
32-bit ARM Cortex-M3 microcontroller
LCD
LPC1850/30/20/10
(1)
MMC
SD/
(1)
64/96 kB LOCAL SRAM
40 kB LOCAL SRAM
16 kB AHB SRAM
APB, RTC DOMAIN
masters
32 kB AHB SRAM
16 kB AHB SRAM
AHB REGISTER
PERIPHERALS
CONTROLLER
INTERFACES,
EXTERNAL
32 kB ROM
slaves
MEMORY
© NXP B.V. 2011. All rights reserved.
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