IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 128
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
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T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Programming Information
IDT82V3288
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
AUTO_BW_SEL
6 - 4
2 - 0
Bit
7
3
7
AUTO_BW_SEL
T0_LIMT
Name
-
-
6
-
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
stages. (default)
Reserved.
This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
Reserved.
5
-
4
-
128
T0_LIMT
3
Description
2
-
1
-
March 14, 2007
0
-
WAN PLL
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