IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 56
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
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5.4
Table 38: Read Timing Characteristics in Motorola Mode
Microprocessor Interface
IDT82V3288
Note:
* Timing with RDY. If RDY is not used, t
Symbol
t
t
t
t
t
t
t
t
t
pw1
pw2
t
t
t
t
su1
su2
t
t
out
T
d1
d2
d3
d4
h1
h2
h3
r1
TI
in
MOTOROLA MODE
Time between consecutive Read-Read or Read-Write accesses
AD[7:0]
A[6:0]
RDY
CS rising edge to AD[7:0] high impedance delay time
WR
CS
Valid address after CS rising edge hold time
pw1
CS rising edge to RDY release delay time
Valid CS after RDY falling edge hold time
Valid WR after CS rising edge hold time
Valid address to valid CS setup time
is 3.5T +10.
One cycle time of the master clock
( CS rising edge to CS falling edge)
Valid CS to valid RDY delay time
Valid WR to valid CS setup time
Valid CS to valid data delay time
Valid RDY pulse width high
High-Z
Valid CS pulse width low
Delay of output pad
High-Z
Delay of input pad
RDY release time
Parameter
Figure 21. Motorola Read Timing Diagram
t
su1
t
su2
t
d2
t
address
d1
56
t
pw2
t
pw1
4.5T + 10 *
data
4.5T + 10
Min
> T
t
0
0
0
0
0
h3
t
h1
t
t
d3
d4
t
12.86
h2
Typ
13
13
10
5
5
3
t
r1
High-Z
High-Z
3.5T + 10
Max
March 14, 2007
WAN PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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