IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 43

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

Table 28: Synchronization Control
3.13.2
FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and
2K_EN bits respectively. They are CMOS outputs.
are aligned with the output clock. They can be synchronized to one of
the three frame sync input signals.
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
Table
Table 27: Frame Sync Input Signal Selection
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signals. The exter-
nal sync alarm is cleared once the selected frame sync input signal with
Functional Description
IDT82V3288
SYNC_BYPASS T0 Selected Input Clock
Figure 9. On Target Frame Sync Input Signal Timing
An 8 kHz and a 2 kHz frame sync signals are output on the
The two frame sync signals are derived from the T0 APLL output and
One of the three frame sync input signals is selected, as determined
If the selected frame sync input signal with respect to the T0 selected
sync input signal
Selected frame
SYNC_BYPASS
output signals
Output clocks
Frame sync
27:
T0 selected
input clock
0
1
0
1
FRAME SYNC OUTPUT SIGNALS
any of IN1 ~ IN3, IN5, IN7,
IN8, IN10 ~ IN14
don’t-care
IN4 or IN6
AUTO_EXT_SYNC_EN
none
IN9
don’t-care
0
1
Selected Frame Sync Input
don’t-care
EX_SYNC1
EX_SYNC1
EX_SYNC2
EX_SYNC3
Signal
none
EXT_SYNC_EN
0
1
1
43
respect to the T0 selected input clock is within the limit. If it is within the
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 28
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting the sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1,
2 or 3 corresponding to EX_SYNC1, EX_SYNC2 or EX_SYCN3 respec-
tively) will compensate this early/late. Refer to
frame sync input signal is in external sync alarm status. The external
sync alarm is indicated by the EX_SYNC_ALARM
EX_SYNC_ALARM
will trigger an interrupt.
by setting the 8K_INV and 2K_INV bits respectively. The frame sync out-
puts can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL
and 2K_PUL bits respectively. When they are pulsed, the pulse width is
defined by the period of OUT3; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 2K_8K_PUL_POSITION bit.
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing
When the selected frame sync input signal is enabled to synchronize
The 8 kHz and the 2 kHz frame sync output signals can be inverted
The EX_SYNC_ALARM_MON bit indicates whether the selected
sync input signal
Selected frame
output signals
Output clocks
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
Frame sync
T0 selected
input clock
for details.
2
bit is ‘1’, the occurrence of the external sync alarm
Synchronization
Disabled
Enabled
Enabled
Figure 9
March 14, 2007
to
Figure
1
WAN PLL
bit. If the
12.