IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 17

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

Table 1: Pin Description (Continued)
Pin Description
IDT82V3288
ALE / SCLK
AD0 / SDO
Name
TRST
RDY
TMS
TCK
AD1
AD2
AD3
AD4
AD5
AD6
AD7
WR
RD
Pin No.
C10
C12
B10
A11
A12
B11
A13
B12
A15
B13
C11
C9
C1
E3
F1
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
pull-up
I/O
I/O
O
I
I
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
JTAG (per IEEE 1149.1)
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the micro-
processor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microproces-
sor interface.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to ini-
tiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
RD: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
17
Description
1
March 14, 2007
WAN PLL