IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 47

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

3.17
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switch power supplies and
the high switching noise from the outputs to the internal PLL. The
82V3288 provides separate VDDA power pins for the internal analog
PLL, VDD_DIFF, VDD_155 and VDD_622 for the high-speed output
driver circuits and VDDD and VDD_AMI pins for the core logic as well as
I/O driver circuits.
ing regulator, the power supply output should be filtering with sufficient
bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic)
capacitors to filter out the switching transients.
VDD_622, VDD_AMI and VDDD are handled individually. VDDA,
VDD_DIFF, VDD_155, VDD_622, VDD_AMI and VDDD should be indi-
vidually connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. Figure 14 illustrated how bypass
capacitor and ferrite bead should be connected to power pins.
Functional Description
IDT82V3288
To achieve optimum jitter performance, power supply filtering is
To minimize switching power supply noise generated by the switch-
For the 82V3288, the decoupling for VDDA, VDD_DIFF, VDD_155,
POWER SUPPLY FILTERING TECHNIQUES
3.3V
3.3V
SLF7028T-100M1R1
SLF7028T-100M1R1
10 µF
10 µF
0. 1 µF
Figure 14. IDT82V3288 Power Decoupling Scheme
0.1 µF
0.1 µF
16 0.1uF capacitors
27 0.1uF capacitors
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
47
VDD_DIFF
VDD_155
VDD_622
VDDA, VDD_DIFF, VDD_155 and VDD_622 should have low imped-
ance. This can be achieved by using one 10 uF (1210 case size,
ceramic) and at least sixteen 0.1 uF (0402 case size, ceramic) capaci-
tors in parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be
placed right next to the VDDA, VDD_DIFF, VDD_155 and VDD_622 pins
as close as possible. Note that the 10 uF capacitor must be of 1210
case size, and it must be ceramic for lowest ESR (Effective Series
Resistance) possible. The 0.1uF should be of case size 0402, this offers
the lowest ESL (Effective Series Inductance) to achieve low impedance
towards the high speed range.
size, ceramic) and one 10 uF (1210 case size, ceramic) capacitors are
recommended. The 0.1 uF capacitors should be placed as close to the
VDDD and VDD_AMI pins as possible.
VDD_AMI
VDDA
VDDD
The analog and high-speed output driver circuits power supply
For VDDD and VDD_AMI, at least twenty-seven 0.1 uF (0402 case
Please refer to evaluation board schematic for details.
IDT82V3288
D2, D4, E2,
K4, L4, A6,
D7, D8
R9, R10,
R12, R13
M2, N2
R6, R7
F2, F4, G3, J1, K2, H2,
H3, M13, M16, N13, P14,
F16, H16, J13, K13, K16,
A10, D12, D13, F14, A8,
B8, D10, A2, A4
P3, T3
J15, K3, K7, K8, K9, K10,
M14, N3, N4, N5, N6, N7,
P8, P9, P10, R3, R5, R8,
N15, P1, P2, P5, P6, P7,
C7, C8, D1, D5, D6, D9,
B1, B3, B5, B7, B9, C2,
H8, H9, H10, H13, H14,
N8, N9, N10, N11, N12,
D11, E4, E13, F13, G2,
K14, L13, L15, M3, M4,
R11, R15, T5, T8, T11,
G13, G15, H1, H4, H7,
J2, J4, J7, J8, J9, J10,
G4, G7, G8, G9, G10,
T14
GND
March 14, 2007
WAN PLL