IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 3

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

FEATURES .............................................................................................................................................................................. 9
APPLICATIONS....................................................................................................................................................................... 9
DESCRIPTION....................................................................................................................................................................... 10
FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11
1 PIN ASSIGNMENT ........................................................................................................................................................... 12
2 PIN DESCRIPTION .......................................................................................................................................................... 13
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 20
Table of Contents
3.1 RESET ........................................................................................................................................................................................................... 20
3.2 MASTER CLOCK & MASTER CLOCK MONITORING ................................................................................................................................ 20
3.3 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 21
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 22
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 24
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 26
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 28
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 30
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 32
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 35
HIGHLIGHTS.................................................................................................................................................................................................... 9
MAIN FEATURES ............................................................................................................................................................................................ 9
OTHER FEATURES ......................................................................................................................................................................................... 9
3.3.1
3.3.2
3.5.1
3.5.2
3.5.3
3.6.1
3.6.2
3.6.3
3.7.1
3.7.2
3.7.3
3.8.1
3.8.2
3.8.3
3.9.1
3.9.2
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 35
Input Clocks .................................................................................................................................................................................... 21
Frame SYNC Input Signals ............................................................................................................................................................ 21
LOS Monitoring .............................................................................................................................................................................. 24
Activity Monitoring ......................................................................................................................................................................... 24
Frequency Monitoring ................................................................................................................................................................... 25
External Fast Selection (T0 only) .................................................................................................................................................. 26
Forced Selection ............................................................................................................................................................................ 27
Automatic Selection ....................................................................................................................................................................... 27
T0 / T4 DPLL Locking Detection ................................................................................................................................................... 28
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
Locking Status ............................................................................................................................................................................... 28
Phase Lock Alarm (T0 only) .......................................................................................................................................................... 29
Input Clock Validity ........................................................................................................................................................................ 30
Selected Input Clock Switch ......................................................................................................................................................... 30
3.8.2.1
3.8.2.2
Selected / Qualified Input Clocks Indication ................................................................................................................................ 31
T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 32
T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 34
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 35
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 35
3.10.1.3 Locked Mode .................................................................................................................................................................... 35
Fast Loss .......................................................................................................................................................................... 28
Coarse Phase Loss .......................................................................................................................................................... 28
Fine Phase Loss ............................................................................................................................................................... 28
Hard Limit Exceeding ....................................................................................................................................................... 28
Revertive Switch ............................................................................................................................................................... 30
Non-Revertive Switch (T0 only) ........................................................................................................................................ 31
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Table of Contents
March 14, 2007