IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 13

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

2
Table 1: Pin Description
Pin Description
IDT82V3288
BOS_MODE0
SONET/SDH
FF_SRCSW
OSCI_MON
T0_LOCK
T4_LOCK
T0_LPF
T4_LPF
MS/SL
Name
OSCI
PIN DESCRIPTION
Pin No.
R16
E14
E15
G1
A1
D3
K1
C3
B2
J3
pull-down
pull-down
pull-down
pull-up
I/O
O
O
O
O
I
I
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
Global Control Signal
BOS_MODE0: Function Application Control
The device supports two applications, as controlled by this pin:
High: Master / Slave application;
Low: Line Card application.
Refer to
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
OSCI_MON: Crystal Oscillator Master Clock Monitoring
A 12.8 MHz clock is input on this pin to monitor the master clock.
Refer to
T0_LPF: T0 APLL External RC (Resistor-Capacitor) Filter Connection
This pin connects an external RC filter to GND.
T4_LPF: T4 APLL External RC (Resistor-Capacitor) Filter Connection
This pin connects an external RC filter to GND.
T0_LOCK: T0 DPLL Phase Locking Status Indication
This pin indicates the T0 DPLL phase locking status.
When the T0 DPLL is phase locked to the T0 selected input clock, this pin is high; otherwise,
it is low.
This pin corresponds to the status indication in the T0_DPLL_LOCK bit (b3, 52H)
T4_LOCK: T4 DPLL Phase Locking Status Indication
This pin indicates the T4 DPLL phase locking status.
When the T4 DPLL is phase locked to the T4 selected input clock, this pin is high; otherwise,
it is low.
This pin corresponds to the status indication by the T4_DPLL_LOCK bit (b6, 52H).
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH)
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is config-
ured as the Master or as the Slave. Refer to
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
Chapter 4 Typical Application
Chapter 3.2 Master Clock & Master Clock Monitoring
13
for details.
Description
Chapter 3.14 Master / Slave Configuration
1
for details.
March 14, 2007
WAN PLL
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