IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 18

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

Table 1: Pin Description (Continued)
Pin Description
IDT82V3288
VDD_DIFF1
VDD_DIFF2
VDD_AMI
VDD_155
VDD_622
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
VDDD7
VDDD8
VDDA1
VDDA2
VDDA3
Name
GND
TDO
TDI
F16, H16, J13, K13, K16
B1, B3, B5, B7, B9, C2,
C7, C8, D1, D5, D6, D9,
D11, E4, E13, F13, G2,
G4, G7, G8, G9, G10,
G13, G15, H1, H4, H7,
H8, H9, H10, H13, H14,
J2, J4, J7, J8, J9, J10,
J15, K3, K7, K8, K9,
K10, K14, L13, L15, M3,
M4, M14, N3, N4, N5,
N6, N7, N8, N9, N10,
N11, N12, N15, P1, P2,
P5, P6, P7, P8, P9, P10,
R3, R5, R8, R11, R15,
T5, T8, T11, T14
M13, M16, N13,P14
A10, D12, D13, F14
A8, B8, D10
D2, D4, E2
A6, D7, D8
F2, F4, G3
R12, R13
R9, R10
Pin No.
M2, N2
H2, H3
R6, R7
A2, A4
P3, T3
J1, K2
K4, L4
L2
L1
Ground
pull-up
Power
Power
Power
Power
Power
Power
Power
I/O
O
I
CMOS
CMOS
Type
-
-
-
-
-
-
-
-
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to
VDDDn: 3.3 V Digital Power Supply
Each VDDDn (group) should be paralleled with ground through a 0.1 µF capacitor.
VDDAn: 3.3 V Analog Power Supply
Each VDDAn group should be paralleled with ground through a 0.1 µF capacitor.
VDD_AMI: 3.3 V Power Supply for AMI I/O
VDD_DIFF1: 3.3 V Power Supply for OUT6
VDD_DIFF2: 3.3 V Power Supply for OUT7
VDD_155: 3.3 V Power Supply for OUT155
VDD_622: 3.3 V Power Supply for OUT622
GND: Ground
Power & Ground
18
Description
Chapter 3.8.1 Input Clock Validity
1
March 14, 2007
for details.
WAN PLL