IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 20

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

Table 2: Related Bit / Register in Chapter 3.2
3
3.1
default value or status.
50 µs. After the RST pin is pulled high, the device will still be in reset
state for 500 ms (typical). If the RST pin is held low continuously, the
device remains in reset state.
3.2
input on the OSCI pin. This clock is provided for the device as a master
clock. The master clock is used as a reference clock for all the internal
circuits. A better active edge of the master clock is selected by the
OSC_EDGE bit to improve jitter and wander performance.
Functional Description
IDT82V3288
The reset operation resets all registers and state machines to their
After power on, the device must be reset for normal operation.
For a complete reset, the RST pin must be asserted low for at least
A nominal 12.8000 MHz clock, provided by a crystal oscillator, is
NOMINAL_FREQ_VALUE[23:0]
OSCI_ALARM
OSCI_ALARM
FUNCTIONAL DESCRIPTION
RESET
MASTER CLOCK & MASTER CLOCK MONI-
TORING
OSC_EDGE
OSCI_SW
Bit
1
2
NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
INTERRUPTS3_ENABLE_CNFG
20
INTERRUPTS3_STS
pin.
NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within
±741 ppm.
the OSCI_MON pin, the master clock on the OSCI pin will be monitored
by the clock on the OSCI_MON pin after the two clocks are stable for 1
second. If the master clock on the OSCI pin does not toggle for 5 contin-
uous 12.8 MHz cycles, it will be considered a failed clock. In this case, if
the OSCI_SW bit is ‘0’, the clock on the OSCI_MON pin replaces the
one on the OSCI pin to be the master clock, and all the outputs of the
device are low; if the OSCI_SW bit is ‘1’, the device operates abnor-
mally.
set. If the OSCI_ALARM
input on the OSCI_MON pin.
GR-253-CORE, ITU-T G.812 and G.813 criteria.
In fact, an offset from the nominal frequency may input on the OSCI
If a 12.8 MHz clock provided by another crystal oscillator is input on
When the clock on the OSCI pin fails, the OSCI_ALARM
The master clock on the OSCI pin will not be monitored if no clock is
The performance of the master clock should meet GR-1244-CORE,
Register
This
offset
can
2
bit is ‘1’, an interrupt will be generated.
be
compensated
by
March 14, 2007
Address (Hex)
setting
06, 05, 04
1
WAN PLL
bit will be
0A
0F
12
the