IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 5
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 153
IDT82V3288
8.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 152
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 152
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 152
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 153
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 153
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 154
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 160
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 163
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 164
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 165
ORDERING INFORMATION .......................................................................................................................................... 170
9.3.1
9.3.2
9.3.3
AMI Input / Output Port ................................................................................................................................................................ 154
9.3.1.1
9.3.1.2
9.3.1.3
CMOS Input / Output Port ............................................................................................................................................................ 156
PECL / LVDS Input / Output Port ................................................................................................................................................ 157
9.3.3.1
9.3.3.2
Structure ......................................................................................................................................................................... 154
I/O Level ......................................................................................................................................................................... 154
Over-Voltage Protection ................................................................................................................................................. 156
PECL Input / Output Port ................................................................................................................................................ 157
LVDS Input / Output Port ................................................................................................................................................ 159
5
March 14, 2007
WAN PLL