IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 48
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
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4
Line Card application, as determined by the BOS_MODE0 pin:
4.1
device.
Typical Application
IDT82V3288
The device supports two applications: Master / Slave application and
The application of the device is shown in
Master / Slave application is only supported by the T0 path of the
• high - Master / Slave application;
• low - Line Card application.
TYPICAL APPLICATION
MASTER / SLAVE APPLICATION
MHz and other
Typical 19.44
or other Equipment
Line Timing
OC-N clock
Timing System
SDH/SONET
and other OC-N clock
Typical 19.44 MHz
155.52 Mbit/s
IDT82V3288
Line Card
2/3E/3/SMC/SEC
Timing Module
Stratum 2/3E
IDT82V3288
IDT82V3288
Figure 15:
BITS/SSU
Stratum
Module
Figure 15. Typical Application
. . .
Typical 8 kHz/1.544 MHz/2.048 MHz
(Primary Reference Source)
622.08 Mbit/s
IDT82V3288
Line Card
Central Clock
Master/Slave
Modules
PRS
48
Of the two devices, one is configured as the Master and the other is con-
figured as the Slave. Refer to
for details.
In Master / Slave application, two devices should be used together.
IDT82V3288
Line Card
2.5 Gbit/s
2/3E/3/SMC/SEC
Timing Module
Stratum 2/3E
IDT82V3288
IDT82V3288
BITS/SSU
Stratum
Module
and other OC-N clock
. . .
Chapter 3.14 Master / Slave Configuration
Typical 19.44 MHz
IDT82V3288
Line Card
10 Gbit/s
MHz and other
Typical 19.44
OC-N clock
Line Timing
March 14, 2007
WAN PLL
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