IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 159

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

9.3.3.2
Table 54: LVDS Input / Output Port Electrical Characteristics
Electrical Specifications
IDT82V3288
Figure 34. Recommended LVDS Input Port Line Termi-
Parameter
I
R
∆V
∆V
SA
t
V
V
t
t
∆R
SKEW
V
V
V
V
I
V
TERM
RISE
FALL
R
SAB
IDTH
DIFF
CM
, I
OH
OL
OD
OS
O
OD
OS
O
SB
LVDS Input / Output Port
667 MHz
667 MHz
2 kHz
2 kHz
to
to
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
Change in V
Change in V
External Differential Termination Impedance
Input Common-mode Voltage Range
R
Output Rise time (20% to 80%)
Input Peak Differential Voltage
Output Fall time (20% to 80%)
Differential Output Impedance
O
Input Differential Threshold
Differential Output Voltage
Output Differential Skew
Mismatch between A and B
100 Ω
100 Ω
nation
Output Offset Voltage
Output Voltage High
Output Voltage Low
OD
OS
Output Current
Output Current
between Logic 0 and Logic 1
between Logic 0 and Logic 1
Description
IN6_POS
IN6_NEG
IN5_POS
IN5_NEG
1350
1125
-100
Min
100
925
250
200
200
95
80
0
159
Figure 35. Recommended LVDS Output Port Line Ter-
1200
Typ
100
100
OUT7_NEG
OUT6_POS
OUT6_NEG
OUT7_POS
2400
1475
1100
1275
Max
900
100
105
400
120
300
300
20
25
25
24
12
50
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
50 Ω (transmission line)
mination
Unit
mV
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
pS
pS
pS
Ω
Ω
%
100 Ω
100 Ω
Driver shorted together
Driver shorted to GND
R
R
R
R
R
R
R
R
R
V
V
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
667 MHz
CM
CM
667 MHz
Test Condition
2 kHz
2 kHz
to
= 1.0 V or 1.4 V
= 1.0 V or 1.4 V
March 14, 2007
to
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
= 100 Ω ± 1%
WAN PLL