IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 8
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 22
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 24
Figure 5. External Fast Selection ................................................................................................................................................................................ 26
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 27
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 34
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 43
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 43
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 44
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 44
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 45
Figure 14. IDT82V3288 Power Decoupling Scheme ................................................................................................................................................... 47
Figure 15. Typical Application ...................................................................................................................................................................................... 48
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 51
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 52
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 53
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 54
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 55
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 56
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 57
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 58
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 58
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 59
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 60
Figure 27. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 154
Figure 28. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 154
Figure 29. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 154
Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 154
Figure 31. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 155
Figure 32. Recommended PECL Input Port Line Termination .................................................................................................................................. 157
Figure 33. Recommended PECL Output Port Line Termination ................................................................................................................................ 157
Figure 34. Recommended LVDS Input Port Line Termination .................................................................................................................................. 159
Figure 35. Recommended LVDS Output Port Line Termination ................................................................................................................................ 159
Figure 36. Output Wander Generation ...................................................................................................................................................................... 163
Figure 37. Input / Output Clock Timing ...................................................................................................................................................................... 164
List of Figures
8
March 14, 2007