IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 78
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IDT82V3288BCG
Manufacturer Part Number
IDT82V3288BCG
Description
IC PLL WAN 3E STRATUM 2 208CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3288BCG.pdf
(170 pages)
Specifications of IDT82V3288BCG
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-CABGA
Frequency-max
622.08MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3288BCG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V3288BCG
Manufacturer:
IDT
Quantity:
200
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INTERRUPTS3_STS - Interrupt Status 3
Programming Information
IDT82V3288
Address: 0FH
Type: Read / Write
Default Value: 11010000
EX_SYNC_ALARM
Bit
7
6
5
4
3
2
1
0
7
EX_SYNC_ALARM
INPUT_TO_T4
OSCI_ALARM
AMI2_VIOL
AMI1_VIOL
AMI2_LOS
AMI1_LOS
T4_STS
Name
T4_STS
6
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
This bit indicates whether OSCI fails.
0: Not fails. (default)
1: Fails.
This bit is cleared by writing a ‘1’.
This bit indicates whether all the input clocks for T4 path changes to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
This bit indicates whether IN2 has an AMI violation.
0: Has no AMI violation. (default)
1: Has an AMI violation.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN2 has a LOS error.
0: Has no LOS error. (default)
1: Has a LOS error.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN1 has an AMI violation.
0: Has no AMI violation. (default)
1: Has an AMI violation.
This bit is cleared by writing a ‘1’.
This bit indicates whether IN1 has a LOS error.
0: Has no LOS error. (default)
1: Has a LOS error.
This bit is cleared by writing a ‘1’.
OSCI_ALARM
5
INPUT_TO_T4
4
78
AMI2_VIOL
3
Description
AMI2_LOS
2
AMI1_VIOL
1
March 14, 2007
AMI1_LOS
0
WAN PLL
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