IDT82V3288BCG IDT, Integrated Device Technology Inc, IDT82V3288BCG Datasheet - Page 63

• Manufacturer Part Number: IDT82V3288BCG
• Description: IC PLL WAN 3E STRATUM 2 208CABGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3288BCG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 208-CABGA
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3288BCG

Table 43: Register List and Map (Continued)
Programming Information
IDT82V3288
Address
(Hex)
2A
2B
2C
2E
1F
20
21
22
23
24
25
26
27
28
29
2F
31
32
33
34
IN11_CNFG - Input Clock 11 Configu-
ration
IN12_CNFG - Input Clock 12 Configu-
ration
IN13_CNFG - Input Clock 13 Configu-
ration
IN14_CNFG - Input Clock 14 Configu-
ration
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
IN1_IN2_SEL_PRIORITY_CNFG
Input Clock 1 & 2 Priority Configuration
*
IN3_IN4_SEL_PRIORITY_CNFG
Input Clock 3 & 4 Priority Configuration
*
IN5_IN6_SEL_PRIORITY_CNFG
Input Clock 5 & 6 Priority Configuration
*
IN7_IN8_SEL_PRIORITY_CNFG
Input Clock 7 & 8 Priority Configuration
*
IN9_IN10_SEL_PRIORITY_CNFG
Input Clock 9 & 10 Priority Configura-
tion *
IN11_IN12_SEL_PRIORITY_CNFG -
Input Clock 11 & 12 Priority Configura-
tion *
IN13_IN14_SEL_PRIORITY_CNFG -
Input Clock 13 & 14 Priority Configura-
tion *
FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
All Input Clocks Configuration
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0
Register Name
-
DivN
Input Clock Quality Monitoring Configuration & Status Registers
-
-
-
-
-
-
-
DIRECT_D
DIRECT_D
DIRECT_D
DIRECT_D
Bit 7
IV
IV
IV
IV
-
-
-
-
-
IN10_SEL_PRIORITY[3:0]
IN12_SEL_PRIORITY[3:0]
IN14_SEL_PRIORITY[3:0]
IN2_SEL_PRIORITY[3:0]
IN4_SEL_PRIORITY[3:0]
IN6_SEL_PRIORITY[3:0]
IN8_SEL_PRIORITY[3:0]
LOCK_8K
LOCK_8K
LOCK_8K
LOCK_8K
Bit 6
-
-
-
-
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
BUCKET_SEL[1:0]
Bit 5
63
-
-
-
-
LOWER_THRESHOLD_0_DATA[7:0]
UPPER_THRESHOLD_0_DATA[7:0]
BUCKET_SIZE_0_DATA[7:0]
PRE_DIVN_VALUE[7:0]
Bit 4
-
-
-
-
PRE_DIVN_VALUE[14:8]
Bit 3
-
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
PRE_DIV_CH_VALUE[3:0]
IN13_SEL_PRIORITY[3:0]
IN11_SEL_PRIORITY[3:0]
IN1_SEL_PRIORITY[3:0]
IN3_SEL_PRIORITY[3:0]
IN5_SEL_PRIORITY[3:0]
IN7_SEL_PRIORITY[3:0]
IN9_SEL_PRIORITY[3:0]
Bit 2
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
IN_FREQ[3:0]
-
DECAY_RATE_0_DATA
Bit 1
[1:0]
Bit 0
March 14, 2007
WAN PLL
Reference
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P 101
P 102
P 103
P 105
P 105
P 105
P 106
P 104
P 104
Page
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