EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 110

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–2
Cyclone IV I/O Elements
Figure 6–1. Cyclone IV IOEs in a Bidirectional I/O Configuration for SDR Mode
Cyclone IV Device Handbook, Volume 1
Interconnect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Cyclone IV I/O elements (IOEs) contain a bidirectional I/O buffer and five registers
for registering input, output, output-enable signals, and complete embedded
bidirectional single-data rate transfer. I/O pins support various single-ended and
differential I/O standards.
The IOE contains one input register, two output registers, and two output-enable (OE)
registers. The two output registers and two OE registers are used for DDR
applications. You can use input registers for fast setup times and output registers for
fast clock-to-output times. Additionally, you can use OE registers for fast
clock-to-output enable timing. You can use IOEs for input, output, or bidirectional
data paths.
Figure 6–1
operation.
Chip-Wide Reset
shows the Cyclone IV devices IOE structure for single data rate (SDR)
OE
clkout
oe_out
aclr/prn
clkin
oe_in
preset
sclr/
Output Register
OE Register
ENA
ENA
D
D
ACLR
/PRN
ACLR
/PRN
Q
Q
Input Register
ENA
D
ACLR
/PRN
Current Strength Control
Q
Slew Rate Control
Open-Drain Out
Pin Delay
Output
Input Register
or Input Pin to
Logic Array
Input Pin to
Delay
Delay
Chapter 6: I/O Features in Cyclone IV Devices
V
CCIO
© December 2010 Altera Corporation
V
CCIO
Cyclone IV I/O Elements
Programmable
Resistor
Pull-Up
Bus Hold