EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 384

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–18
Dynamic Reconfiguration Reset Sequences
Reset Sequence in PLL Reconfiguration Mode
Cyclone IV Device Handbook, Volume 2
When using dynamic reconfiguration in data rate divisions in PLL reconfiguration or
channel reconfiguration mode, use the following reset sequences.
Use the example reset sequence shown in
reconfiguration controller to change the data rate of the transceiver channel. In this
example, PLL dynamic reconfiguration is used to dynamically reconfigure the data
rate of the transceiver channel configured in Basic ×1 mode with the receiver CDR in
automatic lock mode.
Figure 2–11. Reset Sequence When Using the PLL Dynamic Reconfiguration Controller to Change
the Data Rate of the Transceiver Channel
Notes to
(1) The pll_configupdate and pll_areset signals are driven by the ALTPLL_RECONFIG megafunction. For
(2) For t
As shown in
dynamic reconfiguration controller to change the configuration of the PLLs in the
transmitter channel:
1. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset
Reset and Control Signals
signals. The pll_configupdate signal is asserted (marker 1) by the
ALTPLL_RECONFIG megafunction after the final data bit is sent out. The
pll_reconfig_done signal is asserted (marker 2) to inform the
ALTPLL_RECONFIG megafunction that the scan chain process is completed. The
ALTPLL_RECONFIG megafunction then asserts the pll_areset signal (marker
3) to reset the transceiver PLL.
more information, refer to
Cyclone IV Dynamic Reconfiguration
Output Status Signals
pll_configupdate (1)
LTD_Auto
Figure
pll_reconfig_done
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
pll_areset (1)
pll_locked
duration, refer to the
2–11:
Figure
2–11, perform the following reset procedure when using the PLL
1
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices
2
Cyclone IV Device Datasheet
chapter.
3
Figure 2–11
Chapter 2: Cyclone IV Reset Control and Power Down
chapter.
4
Five parallel clock cycles
when you use the PLL dynamic
5
Dynamic Reconfiguration Reset Sequences
© December 2010 Altera Corporation
7
6
t
LTD_Auto
(2)
and the
8