EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 131

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Cyclone IV Devices
Clock Pins Functionality
DC Guidelines
Clock Pins Functionality
High-Speed I/O Interface
© December 2010 Altera Corporation
For the Quartus II software to automatically check for illegally placed pads according
to the DC guidelines, set the DC current sink or source value to Electromigration
Current assignment on each of the output pins that are connected to the external
resistive load.
The programmable current strength setting has an impact on the amount of DC
current that an output pin can source or sink. Determine if the current strength setting
is sufficient for the external resistive load condition on the output pin.
Cyclone IV clock pins have multiple purposes, as per listed:
■
■
■
Cyclone IV E I/Os are separated into eight I/O banks, as shown in
page
side of the device as the transceiver block, as shown in
bank has an independent power supply. True output drivers for LVDS, RSDS,
mini-LVDS, and PPDS are on the right I/O banks. On the Cyclone IV E row I/O banks
and the Cyclone IV GX right I/O banks, some of the differential pin pairs (p and n
pins) of the true output drivers are not located on adjacent pins. In these cases, a
power pin is located between the p and n pins. These I/O standards are also
supported on all I/O banks using two single-ended output with the second output
programmed as inverted, and an external resistor network. True input buffers for
these I/O standards are supported on the top, bottom, and right I/O banks except for
I/O bank 9.
CLK pins—Input support for single-ended and voltage-referenced standards. For
I/O standard support, refer to
DIFFCLK pins—Input support for differential standards. For I/O standard
support, refer to
coupling can be used depending on the interface requirements and external
termination is required. For more information, refer to
Standards Support” on page
REFCLK pins—Input support for high speed differential reference clocks used by
the transceivers in Cyclone IV GX devices. For I/O support, coupling, and
termination requirements, refer to
6–17.
Cyclone IV GX I/Os are separated into six user I/O banks with the left
Table 6–3 on page
6–27.
Table 6–3 on page
Table 6–10 on page
6–12. When used as DIFFCLK pins, DC or AC
6–12.
Figure 6–10 on page
6–28.
Cyclone IV Device Handbook, Volume 1
“High-Speed I/O
Figure 6–9 on
6–18. Each
6–23