EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 375
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CE6E22C8N
Manufacturer Part Number
EP4CE6E22C8N
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE6E22C8N
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
270000
Number Of I /o
91
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-EQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE6E22C8N
Manufacturer:
AD
Quantity:
1 200
Company:
Part Number:
EP4CE6E22C8N
Manufacturer:
ALTERA
Quantity:
648
Part Number:
EP4CE6E22C8N
Manufacturer:
ALTERA
Quantity:
20 000
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 375 of 478
- Download datasheet (13Mb)
Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
Figure 2–5. Sample Reset Sequence for Bonded Configuration Receiver and Transmitter Channels—Receiver CDR in Manual
Lock Mode
Notes to
(1) For t
(2) The number of rx_locktorefclk[n] and rx_locktodata[n] signals depend on the number of channels configured. n=number of
(3) For t
(4) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In subsequent reset sequences, the
© December 2010 Altera Corporation
(rxurstpma) rx_analogreset
channels.
busy signal is asserted and deasserted only if there is a read or write operation to the ALTGX_RECONFIG megafunction.
(rxurstpcs) rx_digitalreset
(txurstpcs) tx_digitalreset
Output Status Signals
CDR Control Signals
rx_locktorefclk[n] (2)
LTD_Manual
LTR_LTD_Manual
Figure
rx_locktodata[n] (2)
rx_locktorefclk[0]
rx_locktodata[0]
Reset Signals
2–5:
pll_locked
pll_areset
duration, refer to the
busy (4)
duration, refer to the
1
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. When the
receiver CDR is in manual lock mode, use the reset sequence shown in
As shown in
in manual lock mode configuration:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the input reference clock.
1 µs
Cyclone IV Device Datasheet
2
Cyclone IV Device Datasheet
Figure
3
2–5, perform the following reset procedure for the receiver CDR
Two parallel clock cycles
4
5
chapter.
6
chapter.
t
LTR_LTD_Manual
(3)
7
7
7
7
t
LTD_Manual
(1)
Cyclone IV Device Handbook, Volume 2
8
Figure
2–5.
2–9
Related parts for EP4CE6E22C8N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: