EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 368

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–2
Table 2–1. Transceiver Channel Reset Signals
Table 2–2. Transceiver Block Power-Down Signals (Part 1 of 2)
Cyclone IV Device Handbook, Volume 2
tx_digitalreset
rx_digitalreset
rx_analogreset
Note to
(1) Assert this signal until the clocks coming out of the multipurpose PLL and receiver CDR are stabilized. Stable parallel clocks are essential for
pll_areset
gxb_powerdown
pll_locked
proper operation of transmitter and receiver phase-compensation FIFOs in the PCS.
Table
Signal
2–1:
Signal
Table 2–1
Table 2–2
(1)
(1)
Resets the transceiver PLL. The pll_areset signal is asserted in two conditions:
■
■
Powers down the entire transceiver block. When this signal is asserted, this signal powers
down the PCS and PMA in all the transceiver channels.
This signal operates independently from the other reset signals. This signal is common to
the transceiver block.
A status signal. Indicates the status of the transmitter multipurpose PLLs or general
purpose PLLs.
■
lists the reset signals available for each transceiver channel.
lists the power-down signals available for each transceiver block.
■
■
■
■
■
■
During reset sequence, the signal is asserted to reset the transceiver PLL. This signal is
controlled by the user.
After the transceiver PLL is reconfigured, the signal is asserted high by the
ALTPLL_RECONFIG controller. This signal is not controlled by the user.
A high level—indicates the multipurpose PLL or general purpose PLL is locked to the
incoming reference clock frequency.
Transmitter Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
Receiver Only
Receiver and Transmitter
ALTGX MegaWizard Plug-In
Manager Configurations
Description
Provides asynchronous reset to all digital logic in
the transmitter PCS, including the XAUI transmit
state machine.
The minimum pulse width for this signal is two
parallel clock cycles.
Resets all digital logic in the receiver PCS,
including:
■
■
■
■
■
The minimum pulse width for this signal is two
parallel clock cycles.
Resets the receiver CDR present in the receiver
channel.
The minimum pulse width is two parallel clock
cycles.
XAUI receiver state machines
GIGE receiver state machines
XAUI channel alignment state machine
BIST-PRBS verifier
BIST-incremental verifier
Chapter 2: Cyclone IV Reset Control and Power Down
© December 2010 Altera Corporation
Description
User Reset and Power-Down Signals