EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 343

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–63. Transceiver Channel Datapath and Clocking when Configured in XAUI Mode
Notes to
(1) Channel 1 low-speed recovered clock.
(2) Low-speed recovered clock.
(3) High-speed recovered clock.
© December 2010 Altera Corporation
Figure 1–63
Fabric
FPGA
coreclkout
:
Figure 1–63
XAUI mode.
/2
Phase
Phase
Phase
Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
Rx
Rx
Rx
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
wr_clk
wr_clk
wr_clk
Tx Phase
Tx Phase
Tx Phase
Tx Phase
Comp
Comp
Comp
Comp
FIFO
FIFO
FIFO
FIFO
rd_clk
rd_clk
rd_clk
rd_clk
Order-
Order-
Order-
Order-
Byte
Byte
Byte
Byte
ing
ing
ing
ing
serializer
serializer
serializer
serializer
/2
/2
/2
/2
Byte
Byte
Byte
Byte
De-
De-
De-
De-
wr_clk
wr_clk
wr_clk
wr_clk
Byte Serializer
Byte Serializer
Byte Serializer
Byte Serializer
/2
/2
/2
/2
Transmitter Channel PCS 3
Transmitter Channel PCS 2
Transmitter Channel PCS 1
Transmitter Channel PCS 0
Receiver Channel PCS 3
Decoder
Receiver Channel PCS 2
Decoder
Receiver Channel PCS 1
Decoder
Receiver Channel PCS 0
Decoder
8B/10B
8B/10B
8B/10B
8B/10B
rd_clk
rd_clk
rd_clk
rd_clk
Match
Match
Match
Match
Rate
FIFO
Rate
FIFO
Rate
FIFO
Rate
FIFO
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
8B/10B Encoder
(1)
(1)
(1)
(1)
Deskew
Deskew
Deskew
Deskew
FIFO
FIFO
FIFO
FIFO
(2)
(2)
(2)
(2)
Aligner
Aligner
Aligner
Aligner
Word
Word
Word
Word
Cyclone IV Device Handbook, Volume 2
Deserial-
Deserial-
Deserial-
Deserial-
Transmitter Channel PMA 3
Transmitter Channel PMA 2
Transmitter Channel PMA 1
Transmitter Channel PMA 0
Receiver Channel PMA 3
Receiver Channel PMA 2
Receiver Channel PMA 1
Receiver Channel PMA 0
izer
izer
izer
izer
Serializer
Serializer
Serializer
Serializer
(3)
(3)
(3)
(3)
CDR
CDR
CDR
CDR
low-speed clock
high-speed
clock
high-speed
clock
high-speed
clock
high-speed
clock
CDR clock
CDR clock
CDR clock
CDR clock
1–63