EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 75

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–4. Clock Networks and Clock Control Block Locations in Cyclone IV E Devices
Notes to
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as
(3) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
(4) PLL_3 and PLL_4 are not available in EP4CE6 and EP4CE10 devices.
© December 2010 Altera Corporation
CDPCLK0
CDPCLK1
CLK[3..1]
DPCLK1
DPCLK0
general-purpose I/O (GPIO) pins.
Figure
5–4:
3
The inputs to the clock control blocks on each side of the Cyclone IV GX device must
be chosen from among the following clock sources:
■
■
■
■
PLL_1
PLL_3
(3)
4
(4)
4
Four clock input pins
Ten PLL counter outputs (five from each adjacent PLLs)
Two, four, or six DPCLK pins from the top, bottom, and right sides of the device
Five signals from internal logic
5
Clock
Control
Block (1)
CDPCLK2
CDPCLK7
(2)
(2)
(3)
2
2
4
4
GCLK[19..0]
5
DPCLK[11.10]
DPCLK[3..2]
20
2
2
CLK[15..12]
CLK[11..8]
Clock
Control
Block (1)
Clock
Control
Block (1)
20
20
4
4
DPCLK[9..8]
DPCLK[5..4]
20
GCLK[19..0]
2
2
(3)
2
4
2
4
5
CDPCLK6
CDPCLK3
Clock
Control
Block (1)
(2)
(2)
Cyclone IV Device Handbook, Volume 1
5
PLL_2
PLL_4
(3)
(4)
4
4
4
CDPCLK5
DPCLK7
CLK[7..4]
DPCLK6
CDPCLK4
5–13