EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 85

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
No Compensation Mode
© December 2010 Altera Corporation
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are phase
shifted with respect to the PLL clock input.
Figure 5–13
this mode.
Figure 5–13. Phase Relationship Between PLL Clocks in No Compensation Mode
Notes to
(1) Internal clocks fed by the PLL are phase
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Figure
shows a waveform example of the phase relationship of the PLL clock in
5–13:
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs
(2)
Phase Aligned
-
aligned to each other.
Cyclone IV Device Handbook, Volume 1
5–23