EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 25

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture
High-Speed Transceivers (Cyclone IV GX Devices Only)
Figure 1–1. Transceiver Channel for the Cyclone IV GX Device
Hard IP for PCI Express (Cyclone IV GX Devices Only)
© December 2010 Altera Corporation
Fabric
FPGA
f
f
Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that
can operate independently. These blocks support multiple industry-standard
communication protocols, as well as Basic mode, which you can use to implement
your own proprietary protocols. Each transceiver channel has its own pre-emphasis
and equalization circuitry, which you can set at compile time to optimize signal
integrity and reduce bit error rates. Transceiver blocks also support dynamic
reconfiguration, allowing you to change data rates and protocols on-the-fly.
Figure 1–1
For more information, refer to the
Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)
in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that
implements the PHY-MAC layer, Data Link Layer, and Transaction Layer
functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point
configurations. This pre-verified hard IP block reduces risk, design time, timing
closure, and verification. You can configure the block with the Quartus II software’s
PCI Express Compiler, which guides you through the process step by step.
For more information, refer to the
shows the structure of the Cyclone IV GX transceiver.
Compensation
TX Phase
FIFO
Byte Serializer
Cyclone IV Transceivers Architecture
PCI Express Compiler User
Receiver Channel PCS
Transmitter Channel PCS
8B10B Encoder
Cyclone IV Device Handbook, Volume 1
Guide.
chapter.
Transceiver Channel
Receiver Channel
PMA
PMA
1–11