EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 306

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–26
Transceiver Channel Datapath Clocking
Cyclone IV Device Handbook, Volume 2
Figure 1–27
for REFCLK pins.
Figure 1–27. AC-Coupled Termination Scheme for a Reference Clock
Note to
(1) V
Figure 1–28
configured as a HCSL input.
Figure 1–28. Termination Scheme for a Reference Clock When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
(2) Select values as recommended by the PCIe clock source vendor.
Channel datapath clocking varies with channel configuration options and PCS
configurations. This section describes the clock distribution from the left PLLs for
transceiver channels and the datapath clocking in various supported configurations.
Table 1–7
Table 1–7. PLL Clocks for Transceiver Datapath
CDR clocks
High-speed clock
Low-speed clock
specification.
ICM
Figure
Figure
can be sourced from the 2.5-V supply with a voltage divider circuit (typically two 1-k resistors).
Clock
lists the clocks generated by the PLLs for transceiver datapath.
LVDS, LVPECL, PCML
(1.2 V, 1.5 V, 3.3 V)
1–27:
shows an example of the termination scheme for AC-coupled connections
shows an example termination scheme for the REFCLK pin when
1–28:
PCI Express
REFCLK
(HCSL)
Source
Receiver CDR unit
Transmitter serializer block in PMA
Transmitter PCS blocks
Receiver PCS blocks when rate match FIFO enabled
0.1 μF
0.1 μF
Z
Z
0
0
Rs
Rs
= 50 Ω
= 50 Ω
(2)
(2)
50 Ω
V
ICM
Chapter 1: Cyclone IV Transceivers Architecture
50 Ω
Usage
50 Ω
50 Ω
REFCLK
REFCLK
© December 2010 Altera Corporation
Cyclone IV GX
Transceiver Clocking Architecture
Cyclone IV GX
+
-
REFCLK
(Note 1)