EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 286

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–6
Cyclone IV Device Handbook, Volume 2
The following describes the 8B/10B encoder behavior in reset condition (as shown in
Figure
■
■
■
Figure 1–7. 8B/10B Encoder Behavior in Reset Condition
The encoder supports forcing the running disparity to either positive or negative
disparity with tx_forcedisp and tx_dispval ports.
of tx_forcedisp and tx_dispval port use, where data is shown in hexadecimal
radix.
Figure 1–8. Force Running Disparity Operation
In this example, a series of K28.5 code groups are continuously sent. The stream
alternates between a positive disparity K28.5 (RD+) and a negative disparity K28.5
(RD-) to maintain a neutral overall disparity. The current running disparity at time
n + 1 indicates that the K28.5 in time n + 2 should be encoded with a negative
disparity. Because tx_forcedisp is high at time n + 2, and tx_dispval is low, the
tx_digitalreset
dataout[9..0]
During reset, the 8B/10B encoder ignores the inputs (tx_datain and
tx_ctrlenable ports) from the FPGA fabric and outputs the K28.5 pattern from
the RD- column continuously until the tx_digitalreset port is deasserted.
Upon deassertion of the tx_digitalreset port, the 8B/10B encoder starts with
a negative disparity and transmits three K28.5 code groups for synchronization
before it starts encoding and transmitting data on its output.
Due to some pipelining of the transmitter PCS, some "don't cares" (10'hxxx) are
sent before the three synchronizing K28.5 code groups.
1–7):
clock
Current Disparity
tx_ctrlenable
dataout[9..0]
tx_forcedisp
tx_dispval
K28.5-
txin[7..0]
clock
During reset
K28.5-
RD-
17C
n
K28.5-
n + 1
RD+
283
Don’t cares after reset
xxx
n + 2
RD+
n + 3
17C
RD-
xxx
Chapter 1: Cyclone IV Transceivers Architecture
BC
n + 4
RD+
283
K28.5-
Figure 1–8
Synchronization
n + 5
RD-
© December 2010 Altera Corporation
K28.5+
17C
n + 6
Transmitter Channel Datapath
RD-
shows an example
K28.5-
n + 7
RD+
283
Dx.y+
operation
Normal