EP4CE6E22C8N Altera, EP4CE6E22C8N Datasheet - Page 142

• Manufacturer Part Number: EP4CE6E22C8N
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8N

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 270000
• Number Of I /o: 91
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–34
Differential SSTL I/O Standard Support in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
f
1
Figure 6–18. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA transmitter is used.
Figure 6–19
Figure 6–19. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when an Altera FPGA transmitter is used.
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. Cyclone IV devices support differential
SSTL-2 and SSTL-18 I/O standards. The differential SSTL I/O standard requires two
differential inputs with an external reference voltage (VREF) as well as an external
termination voltage (VTT) of 0.5 × V
The differential SSTL output standard is only supported at PLL#_CLKOUT pins using
two single-ended SSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with
the second output programmed to have opposite polarity. The differential SSTL input
standard is supported on the GCLK pins only, treating differential inputs as two
single-ended SSTL and only decoding one of them.
For differential SSTL electrical specifications, refer to
Termination” on page 6–15
Figure 6–8 on page 6–15
Figure
Figure
LVPECL Transmitter
6–18:
6–19:
shows the LVPECL DC-coupled termination.
Transmitter
LVPECL
shows the differential SSTL Class I and Class II interface.
and the
0.1 µF
0.1 µF
Cyclone IV Device Datasheet
CCIO
50 Ω
50 Ω
Z 0 = 50 Ω
to which termination resistors are connected.
Z 0 = 50 Ω
(Note 1)
(Note 1)
V ICM
Chapter 6: I/O Features in Cyclone IV Devices
100
“Differential I/O Standard
50
50
Ω
Ω
Ω
© December 2010 Altera Corporation
Cyclone IV Device
LVPECL Receiver
High-Speed I/O Standards Support
Cyclone IV Device
LVPECL Receiver
chapter.